With the advent of relatively large, high performance integrated circuit systems, continuing efforts are underway to optimize the packaging topology in order to reduce pack-age-caused delays and skews to a minimum. Moreover, the ever increasing desire and demands for speed and integration are significantly and dramatically increasing the amount of current that needs to be supplied to a module. Accordingly, the current topology employed is rapidly approaching a practical limit with respect to combining signal layers having fine lines and vias with relatively heavy power planes in order to distribute the current to the module.